Semiconductor memory devices can often include precharge circuits. Precharge circuits can serve to precharge and/or equalize conductive lines to a particular potential. Referring now to FIG. 5, a substantial portion of a precharge circuit for a semiconductor memory device is set forth in a block diagram. The precharge circuit is designated by the general reference character 500, and is shown to include sense amplifiers (SA1 and SA2). The sense amplifiers are shown to include p-channel transistors, P500 and P502, and n-channel transistors, N500 and N502. Also included in FIG. 5 are n-channel transistors N504, N506 and N508, redundant memory cells 502, and capacitors C500 and C502. Bit lines are shown as BL1, /BL1, BL2 and /BL2, and a word line is shown as WL. Furthermore, driving signals for the sense amplifiers (SAl and SA2) are shown as SAP and SAN, and RDPBL indicates a precharge stop signal for stopping the precharge of redundant memory cells 502.
It is understood that while FIG. 5 illustrates the precharge circuit for redundant memory cells 502, the precharge circuit for a "normal" (non-redundant) memory cell would have the same structure.
FIG. 4 is a block diagram showing the structure of a selection circuit. The selection circuit selects a precharge output signal , and outputs the signal to the precharge circuit set forth in FIG. 5. The selection circuit is designated by the general reference character 400.
In the circuit of FIG. 4, an address signal Ai is applied to an address buffer 402. In addition an array selection signal CE and a clock signal CLK is applied to an NAND gate 404. The output of NAND gate 404 is an address decision signal ADLST. The ADLST signal is also applied to the address buffer 402. In response to the Ai and ADLST signals, the address buffer 402 outputs an address XAD to a cell array.
In the arrangement of FIG. 4, the address XAD is output to a block selection circuit 406 by way of a buffer 408. The block selection circuit 406 outputs a precharge stop signal PBL to a normal memory cell array (not shown). The address XAD is also sent to a number of X-decoders 410-1 to 410-n by way of another buffer 412. When address XAD corresponds to a normal memory cell array, one of the X-decoders (410-1 to 410-n) will activate a normal word line (WL1 to WLn). The normal word line (WL1 to WLn) will be activated in conjunction with the PBL signal. Moreover, following the activation of a word line (WL1 to WLn) and a precharge signal PBL, a bit line can be selected, and a normal cell accessed for a data read operation or the like.
When address XAD corresponds to a redundant memory cell array, address XAD is decoded by a redundancy decoder 414. Redundancy decoder 414 includes a number of redundant decoders, shown as 416-1 to 416-n. The outputs from redundant decoders (416-1 to 416-n) are applied as inputs to an OR gate 418. The output of OR gate 418 is a redundant cell decode signal RDSEL. The RDSEL signal is applied to block selection circuit 406 and will place the block selection circuit 406 in an output inhibited state. In an output inhibited state, the PBL signal is deactivated. The RDSEL signal will enable a block selection circuit 420, which will output a redundant precharge stop signal RDPBL. The RDPBL signal will be applied to a redundant memory cell array (not shown).
As shown in FIG. 4, the output of each redundant decoder (416-1 to 416-n) is applied to a corresponding redundant X-decoder (422-1 to 422-n) . One of the redundant X-decoders (422-1 to 422-n) can then activate a redundant word line (RDWL1 to RDWLn) in accordance with the input of the RDPBL signal. Once a redundant word line (RDWL1 to RDWLn) is activated, a bit line can be selected, and a redundant cell accessed for a data read operation or the like.
Referring now to FIG. 6, a timing diagram is set forth illustrating the operation of the circuits set forth in FIGS. 4 and 5. Set forth in FIG. 6 are address XAD, redundant cell decode signal RDSEL, redundant precharge stop signal RDPBL, a redundant word line RDWL, drive signals SAN and SAP, and a bit line pair BL and /BL. The operation of a conventional semiconductor memory device will be described by referring to the timing diagram of FIG. 6 in conjunction with FIGS. 4 and 5.
An Ai signal is received by address buffer 402. In addition, in response to clock signal CLK and array selection circuit CE, NAND gate 404 outputs an ADLST signal to address buffer 402. A read cycle is thereby started, and an address XAD is output from address buffer 402 as an applied address. This is represented in FIG. 6 by waveform XAD making a transition. The address XAD is input to redundant decoder 414. When address XAD corresponds to the address of a redundant memory cell, it is detected by one of the redundant decoders (416-1 to 416-n), and by operation of OR gate 418, the RDSEL signal is activated. In the particular arrangement of FIGS. 4-6, the RDSEL signal is active when it is at a logic high level. The RDSEL signal is applied to block selection circuits 406 and 420.
In response to an active RDSEL signal, the output of block selection circuit 406 is inhibited. Simultaneously, the active RDSEL signal enables block selection circuit 420. The activated block selection circuit 420 activates the RDPBL. In the particular arrangement of FIGS. 4-6, the RDPBL signal stops a precharge operation (is active) when low. Thus, for the particular precharge circuit set forth in FIG. 5, when the RDPBL signal goes low, transistors N504 to N508 will be turned off. One result is that bit line BL1 is isolated from bit line /BL1 and bit line BL2 is isolated from bit line /BL2.
Referring again to FIG. 5, once the PBL signal is driven low, and transistors N504 to N508 are turned off, the signal VPL is set to a logic low level and redundant word line RDWL is selected. The redundant word line RDWL of FIG. 5 may be selected by a redundant X-decoder, such as those identified as 422-0 to 422-n in FIG. 4. In such a case the redundant word line RDWL will be driven to a logic high level, as shown in FIG. 6. Following the activation of a redundant word line RDWL, drive signal SAP is driven to a logic high level, and drive signal SAN is driven to a logic low level. This is represented by the SAN, SAP waveform in FIG. 6. With the SAP signal driven high and the SAN signal driven low, a sense amplifier (SAl and SA2, for example) will be turned on. Consequently, a bit line pair will be driven to complementary logic levels. In the particular example of FIG. 6, such an operation is illustrated by the BL, /BL waveform, in which a bit line BL is driven to a logic high level, and a bit line /BL is driven to a logic low level. In this way, data can be read from a redundant memory cell (such as 502).
A problem present in some conventional redundant decoders, such as that set forth in FIG. 4, is the complexity of the circuits, and the delay involved in selecting a redundant memory cell. Selecting a redundant memory cell requires the simultaneous decoding of a redundant memory cell array selection address (to generate a redundant cell decode signal RDSEL), and the decoding of a redundant word line selection address (to activate a redundant word line) . Further, in the generation of the redundant cell decode signal RDSEL, it is necessary to compute the logical sum of each output of the redundancy decoders 416-1 to 416-n. Thus, the selection of a redundant memory cell can take longer than the selection of a normal memory cell.
In light of the delay involved in conventional approaches to selecting redundant memory cells, it would be desirable to improve the overall speed of a memory device by accelerating the access to redundant memory cells.